Modeling of Electrical Overstress in Integrated Circuits formatIsbn:Hardcover 9780792395058 as in local knowledge and MD as in local knowledge and community self definition and engagement Insider Threats in Cyber Security is a cutting edge text presenting IT and non IT facets of insider threats together Modeling of Electrical Overstress in Integrated Circuits presents a comprehensive analysis of EOS ESD related failures in I O protection devices in integrated circuits Fundamental understanding of the physical phenomena leading to device failures under ESD EOS events is needed for the development of device models and CAD tools that can efficiently describe the device behavior up to the onset of thermal failure